项目作者: PXVI

项目描述 :
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
高级语言: Verilog
项目地址: git://github.com/PXVI/std_module.git
创建时间: 2020-05-18T05:00:37Z
项目社区:https://github.com/PXVI/std_module

开源协议:MIT License

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