项目描述 ：
This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.

高级语言： MATLAB

项目主页：

项目地址: git://github.com/muhammadaldacher/Analog-Design-of-Bootstrapped-Switch.git

创建时间： 2019-07-07T22:55:34Z
项目社区：https://github.com/muhammadaldacher/Analog-Design-of-Bootstrapped-Switch
开源协议：
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